The Design Technology Conference will focus on application-oriented design methods for SoC including heterogeneous functions and SiP integration in themselves a very important success factor for European Micro- and Nano- Electronic companies. Exhaustive research and development in this area has been supported by CATRENE and local governments through the past five years. Latest results and exciting highlights from mainly CATRENE projects will form the subjects of this conference.

All CATRENE projects related to electronic system design, to design technology and to manufacturing topics are invited to contribute to the conference. Sessions are made of one tutorial presentation (45 min.) and technical presentations (20 min. each).

Jose Luis Conesa ALPHASIP, E
Bernard Candaele, Thales Group, F
Marcello Coppola, STMicroelectronics, F
Mart Coenen, EMCMCC, NL
Mario Diaz-Nava, STMicroelectronics, F
Manfred Dietrich, FhG, D
Agnes Fritsch, Thales Group, F
Ahmed Jerraya, CEA-LETI, F
Frank Schenkel MunEDA, D
Peter H Koch, CATRENE EU
Paul Merkus Philips, NL
Frédéric Petrot TIMA, F
Ralf Pferdmenges, Infineon, D
Christian Sebeke, Bosch, D
Wolfgang Rosenstiel, U. Tuebingen & FZI, D
Juergen Haase, edacentrum, D
Patrick Blouet , ST, F
Martin Barnasconi, NXP, NL
Eugenio Villar, U. Cantabria, E
Christoph Grimm, FhG-UKL D

June 23rd, 2014
	9:15	Welcoming Opening
	9:30	Keynote: Grenoble’s innovation Ecosystem by Laurent Malier, CEO, CEA-Leti
	10:00	Keynote : Security aware design, by Jean Pierre Tual, Gemalto
	10:30	Break
		Technical Session 1 Reliability of SoCs in Safety Critical Applications Chair : Juergen Haase, edacentrum, D
	11:00	Tutorial : “Safety critical systems – How the industry manages to ensure dependability with new microelectronic technologies” By Florent Miller, Airbus Group Innovations, F
	11:45	"Increasing the reliability of SoCs” By Vincent HUARD, STMicroelectronics, F
	12:05	"Fast wafer level reliability (fWLR) monitoring of product relevant IP blocks” By Rolf Vollertsen, Infineon Technologies, D
	12:30	Lunch
		Technical Session 2 Power and thermal aware design Chair: Armand Castillejo ST
	14:00	Tutorial: "Coarse Grain Power Reduction at RTL level" by Fahim Rahim , Atrenta
	14:45	"Power Mode Selection in FD-SOI Circuits" Edith Beigne / Diego Puschini , LETI
	15:05	"Toward Energy Neutral Operation’s Platform" by Agnes Fristch TCS & Francois Druilhe STM
	15:30	Break
	16:00	Keynote : "Evolution and challenges of multimedia in the connected world" by Laurent Remont, STMicroelectronics
	16:30	Session 3 Panel : What are the next growth areas in multimedia beyond TV, mobiles phones/tablets, STB, ...? Organizer Mario Diaz-Nava Contributors : ST, Technicolor, Orange, …
	17:30	End
	19:30	Social Event: dinner

June 24th, 2014
	08:30	Keynote : Silicon Europe, Veronique Pequignat, AEPI & Isabelle Guillaume Minalogic
		Technical Session 4 : Energy efficient HPC Chair : F Clermidy, ICT Infrastructure
	09:00	Tutorial: "Heterogeneous HPC Systems" Hu Nam Nguyen, Bull
	09:45	"DRAM architecture for energy efficiency" by Norbert Wehn, UKL
	10:05	"Energy Efficient Server" by Denis Dutoit, CEA-LETI
	10:30	Break
		Technical Session 5 : Power Electronics Chair: Paul Merkus Philips
	11:00	"The role of power electronics to ever increased energy efficiency" by Gerald Deboy, Infineon
	11:20	"Evolution of the Smart Power technologies and design techniques toward high density in HV applications" by Giulio Ricotti, ST
	11:40	"SOI substrates technology and process challenges to deliver cost competitive industrial substrates that enable increased circuit performance" by Manuel Sellier, Soitec
	12:05	"High efficiency High Voltage to Low Voltage DC/DC Converter for electrical or hybrid vehicle" by Patrick Dubus, Valeo
	12:30	Lunch
		Technical Session 6 : Design enablement for advanced silicon technologies Chair: Ahmed Jerraya CEATech
	14:00	Tutorial: "FDSOI technology for energy efficient SoC" by Gergio Cesana, ST
	14:45	"Advanced process enablement" by Lyes Djama, Global Founderies
	15:05	"Advanced System Design Enablement" by Patrick Blouet ST, Agnes Fritsch, Thales
	15:30	Break
	16:00	Session 6 Panel: EDA beyond IC design Chair : JM Chateau, ST Contributors : Synopsys, Atrenta, Mentor, Cadence, Magillem, Doceapower
	17:30	Closing

Registration Fees: 250 € (VAT Excl.)

Registration	Organization
INSIGHT OUTSIDE 39 chemin du vieux chêne - 38240 Meylan Tel: +33 825 595 525 (0,15€/min*) - Fax: +33 4 38 38 18 19 Email: contact@letidays.com Web site: http://www.insight-outside.fr Information desk monday to friday from 2:00pm to 5:00pm	CEA-Leti 17 rue des Martyrs F-38054 Grenoble Cedex 9 Contact: Ahmed Jerraya Email: ahmed.jerraya@cea.fr Web site: http://www.leti.fr

(*) Prices starting from fixed line incumbent, a surcharge may be applied by operators, counting the second after the first 45 seconds.

According to France's Personal Data Privacy Act in effect since June 2004, you may send a request in writing to INSIGHT OUTSIDE 39 chemin du vieux chêne, 38240 Meylan / France, or by email webmaster@insight-outside.fr to access your file in order to consult, modify and/or delete your personal information.

© 2005 - 2014 Insight Outside