• Focus

    3-D ICs enable dramatically improved performances at a much lower cost than new leading-edge CMOS technology below 32 nm transistor fabrication. The success of these new ICs depends on the availability of new methodologies and skills that are required to achieve acceptable design quality and productivity. This workshop brings together key actors from semiconductor companies, system design houses and EDA industry to build a vision of the next step in 3D integrated ICs design. Topics addressed are: Applications requiring 3D, interconnect architectures and thermal management for 3D ICs, application partitioning, floorplanning for 3D architectures, modeling, characterization and testing for 3D ICs.

    Program Preview

    D43D will take place from Wednesday June 26, 2pm to Friday June 28, 2pm

    Program includes 2 keynote sessions and 8 Technical sessions. Technical sessions embed User Case Talks, CAD Talks, and technical and scientific talks. Technical sessions topics are the following:

    - 3D Design and Circuits for Heterogeneous Integration
    - Advances in 3D technology and CAD
    - 3D State of Arts
    - 3D Architecture Design for Computing
    - Thermal simulations and design aware in 3D ICs
    - 3D Verification, Test and Design for Test
    - Design Strategies for 3D IC
    - 3D CAD & Design Flows

    Gala Dinner

    Gala Dinner will take place on Wednesday June 26, 8pm

    Co-General Chairs:
    Ahmed Jerraya - CEA LETI
    David Atienza - EPFL

    Co-Program Chairs:
    Pascal Vivet - CEA LETI
    Giovanni Ansaloni - EPFL

    Organisation Chair:
    Marc Belleville - CEA LETI

    D43D 2012, EPFL
    Lausanne, Switzerland

    D43D 2011, Minatec
    Grenoble, France

    D43D 2010, EPFL
    Lausanne, Switzerland

    D43D 2009, Minatec
    Grenoble, France


  • You can consult the list of participants here
  • For further information

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