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15th Leti Annual Review
Design for 3D (D43D)
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Technical Program D43D
Advanced Program
Wednesday, June 26
Opening
1:45pm
Session 1
- 2pm -> 3:30pm
3D Design and Circuits for Heterogeneous Integration
Christian Val
, 3D Plus,
"TSV versus TPV for Sip Applications"
Uwe Köchel and Andy Heinig
, FhG IIS,
"Design methods and Tools for 2.5D Interposerdesign - Demonstrated on an Interposer for WideIO Memory/Processor Integration"
Laurent Dussopt
, CEA-Leti,
"Millimeter-Wave Transceiver Module Integration in 3D Silicon Interposer Technology"
Dinesh Pamunuwa
, Bristol University,
"System Performance Analysis for Heterogeneous 3-D ICs and Emerging Technologies"
Session 2
- 4pm -> 5:45pm
Advances in 3D technology and CAD
Gerd Schlottig
, IBM Zurich,
"Future Micropocessor package architectures -- trends, tasks, technologies
Frank Lee
, TSMC,
"3D ICs: Overcoming the Barriers in Designing ICs in a New Dimension"
Brendan Farley
, Xilinx,
"High Performance Heterogeneous Integration through Die Stacking"
Kazunari Koga
, Zuken,
"The Next Generation EDA System for 3D Design"
Gala dinner in Grenoble down-town
19:30pm
Thursday, June 27
Opening
8:45am
Session 3
- 9 am -> 10:30 am
3D State of Arts
Keynote:
Georg Kimmich,
ST Ericsson
"3D – What Next"
Axel Janch
, KTH,
"Configuration and placement in NoC based 3D stacks"
Ravi Varadarajan
, Atrenta,
"Design enablement of fine-grained partitioned 3D-ICs with high density inter-die interconnects"
Session 4
- 11 am -> 12:40pm
3D Architecture Design for Computing
Eric Flamand,
ST Microelectronics,
"P2012: A New Multi-Core Platform"
Valentin Puente Varona
, UNICAN,
"Core fusion through 3D stacking"
Christian Weis
, University of Kaiserslautern,
"Variation-aware Power Prediction of (3D)-DRAMs"
Frederic Petrot
, TIMA,
"Cost-Efficient Buffer Sizing in Shared-Memory 3D-MPSoCs Using Wide I/O Interfaces"
Eric Guthmuller
, CEA-Leti
"Adaptive cache architecture exploiting 3D stacking in a manycore context"
Session 5
- 2:10pm -> 3:30pm
Thermal simulations and design aware in 3D ICs
Ayse Coskun
, Boston university,
"3D Stacking as an Enabler for Low-Power High-Performance Computing"
Ridha Hamza
, Docea,
"Modeling and simulating dynamic thermal management of 3DIC designs"
Arvind Sridhar
, EPFL,
"GreenCool: an energy-efficient design method for liquid-cooled 3D MPSoCs"
Pablo Garcia Del Valle
, UCM - Madrid,
"Simulation, cosimulation, emulation."
Session 6
- 4pm -> 5:30pm
3D Verification, Test and Design for Test
Stephane Guilhot
, STEricsson,
“3D-DFT challenges and results for a 3D-circuit including a WideIO compatible memory"
Juergen Schloeffel
, Mentor Graphics
"3D DFT solution for Heterogeneous -Technology Assemblies"
Bernhard Lorenz
, Multitest,
"Test Strategies for 3D ICs – Is KGD Good Enough? Is there a KGD?"
Giorgio Di Natale
, LIRMM,
"Manufacturing Test of 3D Stacked ICs: Problems, Solutions and Standards"
Friday, June 28
Opening
8:45am
Session 7
- 9am -> 10:30am
Design Strategies for 3D IC
Keynote:
Luca Benini
, University of Bologna & ETHZ,
"Making 3D happen, one Platform at a Time"
Paul Franzon
, NCSU,
"Early Design for 3DIC"
Davide Bertozzi
, University of Ferrara,
"Illuminating Future 3D Architectures with Optical Networks-on-Chip"
Session 8
- 11am -> 12:30am
3D CAD & Design Flows
Alexis Farcy
, ST Microelectronics,
"Technology and design solutions for 3D integration platform performance assessment"
Steve Smith
, Synopsys,
"3D-IC Design Flow: Ready for Take-off"
Sedrak Sargisian
, Mentor Graphics,
"3D Physical Verification & parasitic extraction for Heterogeneous - Technology Assemblies"
Anna Fontanelli
, Monozukuri,
"IC-Interposer-Package Co-Design to the Rescue"
Gérald Cibrario
, CEA-Leti,
"Fast iteration between 3D technology and design through a PDK generator"
Lunch will be served on Thursday and Friday
You can consult the list of participants
here
For further information
Registration & Accommodation
Organization
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